FEATURES
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typical) shift out frequency
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.

APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register

DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT595 is an 8-stage serial shift register with astorage register and 3-state outputs. The shift register andstorage register have separate clocks.

Data is shifted on the positive-going transitions of theSH_CP input. The data in each register is transferred tothe storage register on a positive-going transition of theST_CP input. If both clocks are connected together, theshift register will always be one clock pulse ahead of thestorage register.

The shift register has a serial input (DS) and a serialstandard output (Q7’) for cascading. It is also providedwith asynchronous reset (active LOW) for all 8 shiftregister stages.The storage register has 8 parallel 3-statebus driver outputs. Data in the storage register appears atthe output whenever the output enable input (OE) is LOW.

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