Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down ModeOperation
Supports Mixed-Mode Signal Operation onAll Ports (5-V Input and Output VoltagesWith 3.3-V VCC)
Bus Hold on Data Inputs Eliminates theNeed for External Pullup/PulldownResistors
Latch-Up Performance Exceeds 250 mA PerJESD 17
ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 1000-V Charged-Device Model (C101)
This 16-bit edge-triggered D-type flip-flop isdesigned for 1.65-V to 3.6-V VCC operation.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load nor drivethe bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lineswithout interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered whilethe outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translatorin a mixed 3.3-V/5-V system environment.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state.
Use of pullup or pulldown resistorswith the bus-hold circuitry is not recommended.The SN74LVCH16374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional busdrivers, and working registers.
It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positivetransition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data(D) inputs.
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