The SAMA5D4 Series is a high-performance, power-efficient Arm® Cortex®-A5 processor-based MPU capable of running at up to 600 MHz. It integrates the Arm NEON™ SIMD engine for accelerated signal processing, multimedia and graphics, as well as a 128 KB L2-Cache for high system performance. The device features the Arm TrustZone® enabling a strong security perimeter for critical software, as well as several hardware security features. The device also features advanced user interface and connectivity peripherals.

The SAMA5D4 devices have three software-selectable low-power modes: Idle, Ultra-low-power, and Backup. In Idle mode, the processor is stopped while all other functions can be kept running at normal operating bus frequency. In Ultralow-power mode, the processor is stopped while all other functions can be kept running at minimum operating bus frequency. In Backup mode, only the real-time clock, real-time timer, backup SRAM, backup registers, and wakeup logic are running.

The SAMA5D4 features an internal multi-layer bus architecture associated with 32 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device supports DDR2/LPDDR/LPDDR2 and SLC/MLC NAND Flash memory with 24-bit ECC.

The comprehensive peripheral set includes a 720p hardware video decoder, an LCD controller with overlays for hardware-accelerated image composition, a resistive touchscreen function, and a CMOS sensor interface. Connectivity peripherals include a dual 10/100 Ethernet MAC with IEEE1588, three HS USB ports, UARTs, SPIs and I2Cs.

Security features include an “on-the-fly” encryption-decryption process from the external DDR memory, tamper detection pins, secure storage of critical data, an integrity check monitor (ICM) to detect modification of the memory contents and a secure boot. The product also includes a dedicated coprocessor for public key cryptography such as RSA and elliptic curves algorithms (ECC), as well as AES, 3DES, SHA function and TRNG. These features protect the system against counterfeiting, safeguard sensitive data, authenticate safe programs and secure external data transfers.

The SAMA5D4 series is optimized for control panel/HMI applications needing video playback and applications that require high levels of connectivity in the industrial and consumer market. Its security features make the SAMA5D4 well suited for secure gateways or for the IoT.

Features

• Arm Cortex-A5 Core

- Armv7-A Thumb2® instruction set

- Arm TrustZone

- NEON Media Processing Engine

- 945 MIPS @ 600 MHz in worst conditions

• Memory Architecture

- Memory Management Unit

- 32 Kbyte Data Cache, 32 Kbyte Instruction Cache

- 128 Kbyte L2 Cache

- One 128 Kbyte scrambled internal ROM single-cycle access at system speed, embedding Microchip boot loader/Microchip Secure boot loader

- One 128 Kbyte scrambled internal SRAM, single-cycle access at system speed

- High-bandwidth scramblable 16-bit or 32-bit Double Data Rate Multi-port Dynamic RAM Controller supporting 512 Mbyte 8-bank DDR2/LPDDR/LPDDR2, including partial areas “on-the-fly” AES encryption/decryption

- EBI (External Bus interface) supporting:

 16-bit NAND Flash controller, including 24-bit error correction code (PMECC) for 8-bit NAND Flash

 Independent Static Memory Controller (SMC) with datapath scrambling

• System running up to 200 MHz in worst conditions

- Power-on Reset Cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and secure Real-time Clock - Internal regulator

- One 600–1200 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed

- Internal Low-power 12 MHz RC Oscillator

- Low-power 32 kHz RC Oscillator

- Selectable 32.768 KHz Low-power oscillator and 12 MHz Oscillator

- Two 64-bit, 16-channel DMA Controllers

- 64-bit Advanced Interrupt Controller

- 64-bit Secure Advanced Interrupt Controller

- Three Programmable External Clock Signals

- Programmable fuse box with 512 fuse bits available for customer, including JTAG protection

• Three Low-power Modes: Idle, Ultra-low-power, and Backup

• Peripherals

- Video Decoder (VDEC) supporting formats MPEG-4, H.264, H.263, VP8 and JPEG, and image postprocessing

- LCD TFT Controller with 4 overlays up to 2048x2048 or up to 720p in video format, with rotation and alpha blending

- ITU-R BT. 601/656 Image Sensor Interface (ISI)

- One High-Speed USB Device, Three High-Speed USB Host with On-chip Transceiver

- Two 10/100 Mbps Ethernet MAC Controllers with IEEE 1588 v2 support

- Software Modem Interface (SMD)

- Two high-speed memory card hosts (eMMC 4.3 and SD 2.0)

- Three Master/Slave Serial Peripheral Interfaces (SPI)

- Five USARTs, two UARTs, one DBGU

- Two Synchronous Serial Controllers (SSC)

- Four Two-wire Interfaces up to 400 Kbits/s supporting I2C protocol and SMBUS (TWI)

- Three 3-channel 32-bit Timer/Counters (TC)

- One 4-channel 16-bit PWM Controller

- One 5-channel 10-bit Analog-to-Digital Converter with Resistive Touchscreen function

• Safety - Internal and external memory integrity monitoring, with Integrity Check Monitor (ICM) based on SHA256

- Power-on Reset Cells - Main Crystal Clock Failure Detector

- Independent Watchdog - Register Write Protection

- Memory Management Unit

• Security

- 512 bits of scrambled and erasable registers(1)

- 8 Kbytes of internal scrambled RAM with non-imprinting support, 6 Kbytes are erasable(1)

- 8 PIOBU tamper pins for static or dynamic intrusion detections(1)

- Microchip secure boot(2) ______________________

• Cryptography

- True Random Number Generator (TRNG), compliant with NIST special publication 800-22 test suite and FIPS PBUs 140-2 and 140-3

- SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) compliant with FIPS publications 180-2

- AES: 256-bit, 192-bit, 128-bit Key Algorithm, compliant with FIPS PUB 197 specifications

- Advanced Encryption Standard Bridge (AESB): AES 128 that includes Automatic Bridge Mode for automatic DDR port Encryption/ Decryption

- TDES: Two-key or Three-key Algorithms, compliant with FIPS PUB 46-3 specifications - Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) for RSA, DSA, ECC GF(2n), ECC GF(p)(1)

• Up to 152 I/Os - Five Parallel Input/Output Controllers with slew rate control on high-speed I/Os

- Input Change Interrupt capability on each I/O Line, selectable Schmitt Trigger input

- Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering

• Packages

- 361-ball stubless TFBGA, 16x16 mm body, pitch 0.8 mm

- 289-ball stubless LFBGA, 14x14 mm body, pitch 0.8 mm